Job DescriptionExperience : 3+ Years
nNotice Period : Immediate to 30 days.
nJob Description:
n
- n
- Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus)n
- Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closuren
- Work closely with design team to come up with preplacement requirements & timing constraintsn
- Work closely with physical design team for floorplan, placement & timing reviewsn
- Work closely with cross-functional teams to review standard cell profile, timing models & memory modelsn

nSkills:
n
- n
- Good understanding of ASIC design flown
- Hands on experience in synthesis and static timing analysisn
- Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a mustn

nExperience in Perl, TCL and shell scripting is desirable
n* Excellent interpersonal & analytical skills with ability to work independently
nBachelors or Master's Degree with a robust VLSI Background

📌 Synthesis Engineer (Vasanthanagar)
🏢 Mirafra Technologies
📍 Vasanthanagar