Job DescriptionLead / Principal Physical Design Engineer (Team Lead)
NLocation: Ahmedabad, India (Sasken Silicon)Function: ASIC Backend / Physical DesignReports to: PD Engineering Manager / Silicon Delivery HeadTeam: Leads a pod of ~10 junior–to–mid PD engineers (PD, STA, DFT, PV)Engagement context: Advanced-node (Intel 18A / sub-3nm) backend programs
NRole Summary
nWe are looking for an experienced Physical Design lead to own the backend implementation of a high-performance digital IP on an advanced process node, from synthesis through tapeout-ready GDS-II. Beyond hands-on technical depth, this person must be able to lead and grow a team of ~10 junior PD engineers — distributing work, reviewing quality, unblocking the team, and driving convergence against tight QoR and schedule targets.
NThis is a delivery-ownership role: the lead is accountable for floorplan strategy, timing/power/area closure, signoff quality, and on-time tapeout, while mentoring less-experienced engineers to operate at advanced-node standards.
NKey Responsibilities
nTechnical ownership
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- Own the full RTL-to-GDS physical design flow: synthesis, floorplanning, placement, CTS, routing, and signoff. N
- Define floorplan and power-delivery strategy, including advanced-node considerations such as backside power delivery (PowerVia) and gate-all-around / RibbonFET cell handling where applicable. N
- Drive timing closure across all PVT corners (MMMC, AOCV/POCV), including setup/hold, signal integrity, and complex timing ECOs. N
- Own physical verification closure (DRC/LVS, antenna, PERC), power/EM/IR integrity, and thermal / self-heating (SHE) signoff. N
- Manage memory and macrointegration (e.G., large SRAM arrays), congestion management, and high pin-density datapath closure. N
- Set up and validate thePD flow on a recent PDK, including tool/flow bring-up and "pipe-clean" trial runs. N

nTeam leadership (critical)
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- Lead a pod of ~10junior PD engineers: assign blocks/tas

📌 Hiring: Lead Engineer (Ahmedabad)
🏢 Sasken Technologies
📍 Ahmedabad