Job Description:
- Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.
- Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.
- Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.
- Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops recent formal verification methodologies.
- Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.
- Finds and implements corrective measures to resolve failing tests.
- Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.
- Maintains and improves existing functional verification infrastructure and methodology.
- Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic.
- Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures.
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Minimum Qualifications: 2-18 years of experience in formal verification
- Preferred Qualifications: • BTech/MTech in Electronics, Electrical or CS
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or