Job Description
STA & Synthesis Lead Engineer
nExperience: 5+ Years
nEducation: B.Tech/B.E./M.Tech/M.E. in VLSI, Electronics, Electrical Eng
nLocation: Bangalore
nWe are looking for an experienced STA & Synthesis Lead Engineer with hands-on experience in Logic synthesis, static timing analysis, timing closure, and design optimization. The ideal candidate will have solid expertise in PPA optimization, MMMC timing analysis, SDC constraints, ECO implementation, and formal equivalence checking, with the ability to work closely with RTL, DFT, and Physical Design teams.
nThe candidate will be responsible for driving synthesis and timing sign-off activities from RTL through implementation, identifying timing bottlenecks, and delivering optimized designs that meet Power, Performance, and Area (PPA) targets.
nKey Responsibilities
n1. Logic Synthesis & PPA Optimization
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- Perform physical-aware RTL-to-gate synthesis for complex digital designs.n
- Optimize synthesis results for Power, Performance, and Area (PPA) targets.n




- Analyze synthesis reports and identify opportunities for timing, area, and power improvements.n
- Work with RTL designers to resolve synthesis-related issues and improve RTL quality.n
- Support synthesis flows across block-level and top-level designs.n

n2. Constraint Development & Management
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- Develop, review, validate, and debug SDC timing constraints for block-level and top-level designs.n
- Define and maintain constraints for functional, scan, and DFT modes.n
- Handle clock definitions, generated clocks, clock relationships, I/O constraints, false paths, multicycle paths, and case analysis.n
- Debug constraint-related timing issues and ensure constraint completeness and correctness.n

n3. Static Timing Analysis & Sign-Off
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- Perform Static Timing Analysis (STA) across Multi-Corner Multi-Mode (MMMC) scenarios.n
- Drive timing sign-off for setup, hold, recovery, removal, and clock-gating checks.n
- Analyze criti

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