Job DescriptionJob Title: Lead DFT Engineer
nExperience: 7+ Years
nLocation: Bangalore
nEmployment Type: Full time
nIndustry: Semiconductors / ASIC / SoC Design
nJob Summary:
nWe are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
nKey Responsibilities:
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- Define and drive DFT strategy and architecture for multiple ASIC/SoC projects.n
- Lead implementation and verification of DFT features like:n
- Scan insertion and compression (e.g., EDT)n
- ATPG pattern generation and fault gradingn
- MBIST and Logic BIST insertion and validationn
- Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687)n
- Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up.n
- Collaborate with RTL, STA, PD, and test engineering teams for seamless integration.n
- Perform pattern generation, fault simulation,



and debug test coverage gaps.n
- Own DFT signoff, timing closure (DFT-related paths), and ATE pattern delivery.n
- Support silicon bring-up, test vector validation on ATE, and yield optimization.n
- Mentor and guide junior DFT engineers; conduct design reviews and training sessions.n
- Develop and maintain DFT automation scripts and infrastructure.n

nRequired Skills and Experience:
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- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design.n
- 7+ years of experience in DFT for complex ASIC or SoC designs.n
- Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.n
- Hands-on experience with DFT tools such as:n
- Synopsys: DFT Compiler, TetraMAX, TestMAXn
- Siemens EDA: Tessent ScanPro, MBIST, IJTAGn
- Cadence/others: Modus, Encounter Testn
- Strong knowledge of RTL design, STA, and synthesis flows.n
- Proficient in scripting languages (Python, Perl, Tc

📌 Lead DFT Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar