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Experience: 5+ yrs

Location: Bengaluru, Hyderabad, Telangana, India

Job Type: Full time

We are looking for an experienced Senior RTL Design Engineer – CPU & Microarchitecture to contribute to the design and development of high-performance ASIC and SoC architectures, with a strong focus on CPU cores and processor subsystems.

The ideal candidate will have deep expertise in RTL design, SystemVerilog, CPU microarchitecture, and computer organization, along with practical experience developing complex digital designs for production silicon. You will contribute to architecture implementation, RTL development, verification collaboration, synthesis readiness, and technical debugging across the SoC development lifecycle.

Requirements

KEY RESPONSIBILITIES
- Design, develop, and maintain synthesizable RTL for CPU cores and processor subsystems.
- Translate CPU microarchitecture specifications into efficient and scalable RTL implementations.




- Develop and optimise instruction execution pipelines, hazard handling, branch prediction, and related CPU datapath/control logic.
- Design and integrate L1/L2 cache, MMU, interrupt, and memory subsystem components.
- Implement and integrate AMBA-based interfaces and interconnect protocols including AXI, AHB, APB, ACE, and CHI.
- Develop high-quality RTL using SystemVerilog, Verilog, and VHDL.
- Participate in microarchitecture reviews, RTL design reviews, and technical design discussions.
- Perform RTL linting, structural analysis, and front-end quality checks using tools such as Synopsys SpyGlass and VCS.
- Support synthesis and design implementation activities using Synopsys Design Compiler or Cadence Genus.
- Collaborate with verification engineers to support functional verification, debug, and design quality.
- Analyse simulation results, identify RTL issues, and drive root-cause resolution.
- Develop scripts and automation u

📌 Senior RTL Design Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru