16 Sep
|
MosChip®
|
Vasanthanagar
16 Sep
MosChip®
Vasanthanagar
Job DescriptionJob Description:
nExperience Level: 6 - 12 Years
nLocation: Bangalore / Hyderabad
nRole: Senior / Lead
nWork Mode: Work from office ( 5 days a week )
nRequired Skills
n
- n
- Experience in Logic design / RTL coding is a must.n
- Experience in SoC design and integration for complex SoCs is a must.n
- Experience in Verilog/System-Verilog is a must.n
- Experience in multi-clock designs and asynchronous interfaces is a must.n
- Experience in using the tools in ASIC development such as Lint and CDC.n
- Experience in Synthesis / Understanding of timing concepts is a plus.n
- Experience in ECO fixes and formal verification.n
- Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.n
- Excellent oral and written communication skills.n
- Proactive, creative, curious, motivated to learn and contribute, with valuable collaboration skillsn
📌 RTL Design Engineer (Vasanthanagar)
🏢 MosChip®
📍 Vasanthanagar