You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow , doing implementation to achieve best in class ASICs , which are optimized for power, performance and area metrics

Responsibilities

- Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
- Working as independent contributor in algorithm development, fixed-point modelling and fixed-point performance verification
- Working with experts of different areas to ensure the most competitive solutions
- Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues
- Supporting HW/SW bring-up and debug

Qualifications





- 8+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
- Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
- Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar
- Scripting experience in TCL, python or Perl
- Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very valuable academics

📌 SoC Physical Design Engineer (India)
🏢 NOKIA
📍 India