Description - DFT Engineer (Senior / Manager) Location: Bangalore

Experience: 3-15 Years

Employment Type: Full-Time

Position Overview

We are looking for experienced DFT Engineers / Senior DFT Engineers / DFT Managers with 3-15 years of experience in the Design-for-Test (DFT) domain.

The ideal candidate should have a solid understanding of DFT concepts and hands-on experience in at least one or more areas such as BSCAN, MBIST, Scan, ATPG, and Simulation . The role involves DFT implementation, simulation, debugging, coverage improvement, cross-functional collaboration, and mentoring of DFT engineers.

Key Responsibilities

- Develop a clear understanding of BSCAN, MBIST, Scan, ATPG, and simulation concepts.
- Work on at least one of the following:

- MBIST Insertion

- Scan Insertion
- ATPG Pattern Generation and Simulation

- MBIST and BSCAN Simulation
- Work with industry-standard DFT tools such as Cadence, Siemens Tessent, and Synopsys.
- Perform Zero Delay and SDF Timing Simulations.
- Debug simulation issues using GUI-based industry-standard simulators such as VCS, NCSim, or Xcelium.
- Work with fault models including:
- Stuck-at Fault

- Transition Delay Fault (TDF)

- IDDQ
- Implement techniques to improve scan test coverage.
- Work on SoC-level DFT, including:

- OCC / OPCG insertion
- EDT / Compression Logic insertion
- Clock module handling for scan purposes
- Support post-silicon bring-up and production activities.
- Work on tester debug activities, including analysis of shmoo plots and graphs.
- Provide test-mode timing constraints to STA and Physical Design (PD) teams.




- Collaborate effectively with cross-functional teams and customer teams.
- Lead, guide, and mentor junior/mid-level DFT engineers.
- Participate in debugging and resolution of complex DFT issues.

Required Skills

- 3-15 years of hands-on experience in DFT / VLSI.
- Strong understanding of BSCAN, MBIST, SCAN, ATPG, and Simulation concepts.
- Hands-on experience in at least one major DFT area such as MBIST, Scan Insertion, ATPG, or DFT Simulation.
- Experience with one or more industry-standard DFT tools:

- Cadence

- Siemens Tessent

- Synopsys
- Experience with simulators such as VCS, NCSim, or Xcelium.
- Good debugging and problem-solving skills.
- Understanding of fault models and test coverage improvement techniques.
- Experience with SoC-level DFT is preferred.
- Strong communication and interpersonal skills.

Good to Have
- Experience with Zero Delay and SDF Timing Simulations.
- Experience with OCC/OPCG and EDT/Compression Logic insertion.
- Exposure to post-silicon bring-up and production activities.
- Experience with tester debugging, shmoo plots, and graphs.
- Experience in providing DFT/test-mode timing constraints to STA and PD teams.
- Experience in leading or mentoring DFT engineers.

Key Competencies
- DFT / VLSI Design
- Scan & ATPG
- MBIST
- BSCAN
- DFT Simulation
- Fault Modeling & Coverage
- SoC-Level DFT
- Debugging & Problem Solving
- Cross-functional Collaboration
- Team Leadership & Mentoring
- Customer Communication

Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or a related engineering discipline preferred.

📌 Senior DFT Engineers (Bengaluru)
🏢 YO IT CONSULTING
📍 Bengaluru