Senior Engineer (Level 1) Position: Senior Engineer (Level 1) : Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off. Be responsible for a comprehensive DFT plan Incumbent to work with DFT and cross functional teams To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field ESSENTIAL SKILLS &
EXPERIENCE Robust fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team player Hands-on experience with DFT implementation using standard EDA and flow is a must.
Experience on latest technology (28nm,16nm,7 nm) Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services Experience Level Senior Level
📌 Senior Design for Test (DFT) Engineer (Bengaluru)
🏢 Arrow Electronics India
📍 Bengaluru
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