We are looking for a Senior Analog Layout Engineer with robust hands-on experience in advanced-node custom/analog layout, particularly 2nm, 3nm, and 5nm FinFET technologies.
Key Responsibilities
- Own block-level analog/custom layout from floorplanning to tapeout. - Develop layouts for analog, mixed-signal and custom circuit blocks. - Work on advanced-node technologies including 2nm/3nm/5nm FinFET. - Apply matching, symmetry, common-centroid, shielding and sensitive-net routing techniques. - Optimize layouts for parasitics, PPA, EM/IR and signal integrity. - Perform and debug DRC, LVS, ERC and PEX. - Analyze layout-dependent effects (LDE) and minimize post-layout performance impact. - Collaborate closely with Analog Design, Circuit Design and Physical Verification teams.
Core Technical Skills
- 4–10 years of relevant Analog/Custom Layout experience. - Strong hands-on experience with Cadence Virtuoso / Custom Layout. - Proven experience in 2nm / 3nm / 5nm FinFET technologies. - Strong understanding of advanced-node design rules and device layout. - Expertise in matching, common-centroid, shielding, guard rings and isolation. - Experience with Calibre/PVS, DRC/LVS/ERC and PEX. - Strong understanding of parasitic extraction and post-layout analysis. - Tapeout experience in advanced technology nodes is highly preferred.
Ideal Profile A hands-on analog layout engineer capable of delivering tapeout-quality custom layouts at advanced FinFET nodes, with strong ownership of layout quality, parasitic optimization and physical verification.