RTL Design Engineer | 5-12 Years /n We are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation. /n Key Requirements: /n /n

- Strong experience in RTL design using Verilog/SystemVerilog or VHDL

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- Hands-on experience in ASIC/SoC development

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- Strong understanding of digital design concepts, including combinational logic, sequential logic, and FSMs

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- Experience in functional verification and RTL debugging

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- Knowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.

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- Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycle

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- Exposure to UVM-based verification environments

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- Experience with Python, Perl, or Shell scripting

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- Familiarity with STA and synthesis flows

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- Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field

/n /n Why Join Us? /n /n

- Prospect to work on cutting-edge ASIC/SoC technologies

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- Collaborative and fast-paced engineering environment

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- Strong learning and career growth opportunities

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- Competitive compensation and benefits package

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📌 RTL Design Engineer Role (Bengaluru)
🏢 HCLTech
📍 Bengaluru