-This role requires a senior-level Physical Design Engineer (5–8years) with end-to-end ownership of block-level PnR and signoff on advanced nodes.
-The engineer is expected to independently drive floor planning, placement, CTS, routing, extraction, STA, and EM/IR closure, consistently meeting aggressive PPA targets for SoC designs.
-The candidate should have proven experience across multiple advanced technology nodes, deep understanding of ASIC PD methodologies, and solid digital design fundamentals.