Job DescriptionRequisition- SoC DFT Lead
NExperience-10+ Years
nLocation- Bangalore
N
- n
- Tessent based SSNinsertion at block or Top level N
- SSN validationn
- SSN insertion expertise N
- Tessent MBIST insertion N
- Responsible for Implementing and integrating scan insertion, scan compression, MBIST, OCC and boundary scan at gate/RTL level. N
- Team Handling Skill is preferred. N

nKey Responsibilities
NSoC DFT Architecture & Leadership
N Own SoC-level DFT architecture and strategy for custom and platform-based
NSoCs.
n Define anddrive DFT implementation plans across multiple concurrent SoC
Nprograms.
n Act asthe technical authority and signoff owner for all DFT-related decisions and
Ndeliverables.
nExecution & Technical Ownership
N Lead DFT RTL integration, scan insertion, and test architecture implementation.
N Own and drive:
N Scan, Compression, and ATPG strategy
N MBIST, BISR, and redundancy implementation
N JTAG / TAP, Boundary Scan, and debug infrastructure
N Ensure DFT readiness across functional, scan, and low-power modes.




N Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and
Nimplementation.
n Drive ATPG pattern generation, simulation, and debug to ensure high test
Ncoverage and quality.
nCross-Functional & Manufacturing Interface
N Work closely with physical design teams to ensure scan and test logic closure
Nwith minimal PPA impact.
N Interface with manufacturing, ATE, and OSAT teams on test requirements, vector
Ndelivery, and silicon bring-up.
N Support post-silicon debug, yield ramp, and test optimization.
N Represent in customer-facing technical discussions related to DFT
Nstrategy and signoff.
nMethodology & Team Development
N Define and standardize DFT methodologies, flows, and checklists across
Nprograms.
n Drive automation, scripting, and reuse to improve DFT efficiency and
Npredictability.
n Mentor and develop DFT engineers and leads, building deep techni

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