Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in physical design.
Experience in high performance synthesis, Place and Route (PnR) and sign-off optimizations. Experience in sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
Experience with programming in TCL/Python.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with constraints, synthesis or Clock Tree Synthesis (CTS).
Experience using Machine Learning (ML) in physical design/signoff convergence (e.g., STA/EMIR closure).
Knowledge of Verilog/SystemVerilog.
Understanding of circuit design, device physics and deep submicron technology.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products.
You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Application Instructions: In most instances, this position requires in-person interviews as part of the hiring process.
As a Physical Design Engineer, you will contribute to improving Design Power, Performance, and Area (PPA) using various techniques. You will use your experience of physical design and machine learning to solve hard technical problems, collaborate with Register-Transfer Level/Design Verification/Design for Testability (RTL/DV/DFT) teams, and improve on Power, Performance, Area and Schedule. You will directly impact logic design and optimizations, floorplan, place and route, clock and power planning, timing analysis, Power Distribution Network (PDN) analysis and beyon
📌 Silicon Physical Design Engineer Bengaluru (India)
🏢 Google
📍 India