Job Description

SRAM Memory Layout Engineer

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Experience: 3–6 Years

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Location: Bangalore

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Notice Period: Immediate to 60 Days

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Technology: TSMC 2nm/3nm | Samsung 2nm/4nm

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Job Description

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We are looking for experienced SRAM Memory Layout Engineers with strong hands-on expertise in advanced-node memory layout and physical verification. The ideal candidate should have experience working on SRAM macros and memory structures from layout development through tape-out.

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Key Responsibilities & Skills

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3–6 years of hands-on experience in SRAM Memory Layout.
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Strong experience with Single Port, Dual Port, Pseudo Dual Port SRAM, Register File, FIFO, and Embedded Memory macros.
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Hands-on experience with TSMC 2nm/3nm and/or Samsung 2nm/4nm technology nodes.
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Develop and integrate bit-cell arrays, sense amplifiers, decoders, column muxes, row/column periphery, and top-level memory blocks.
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Experience across the complete layout lifecycle, including floorplanning, placement, routing, optimization, DRC/LVS/ERC, PEX,



and tape-out.
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Solid knowledge of matching, symmetry, EM/IR, density, antenna, ESD, and advanced-node design rules.
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Proficiency in Cadence Virtuoso and Calibre DRC/LVS/PEX.
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Experience in area, performance, power, yield, and reliability optimization.
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Strong debugging skills with hands-on experience in PV issue resolution and ECO implementation.
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Good scripting skills in Tcl/Python for layout automation and flow improvement will be an added advantage.
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Ability to collaborate effectively with Memory Design, Circuit Design, and Verification teams.
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Preferred Candidate Profile

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Strong understanding of advanced-node SRAM layout methodologies.
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Positive problem-solving and debugging skills.
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Ability to independently handle layout tasks and resolve physical verification issues.
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Solid communication and cross-functional collaboration skills.
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📌 Sram Memory Layout Engineer Bengaluru (India)
🏢 Modernize Chip Solutions (MCS)
📍 India