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Experience: 7+ yrs

Location: Bengaluru, Karnataka

Job Type: Full time

We are looking for a highly experienced RTL Integration Engineer to lead complex SoC and subsystem RTL integration for next-generation semiconductor products. The role requires strong expertise in SystemVerilog/Verilog, digital design, AMBA protocols, static verification, timing constraints, and integration automation.

You will be responsible for integrating multi-million-gate SoCs and complex third-party IPs, ensuring design quality and integration readiness across the development lifecycle. The role involves close collaboration with Architecture, Design Verification, DFT, Synthesis, Physical Design, and other cross-functional teams to resolve integration issues and drive designs toward successful tapeout.

Requirements

KEY RESPONSIBILITIES
- Lead RTL integration of multi-million-gate SoCs, subsystems, and complex third-party IPs.
- Integrate IPs such as PCIe, DDR, Ethernet, ARM/RISC-V cores,



and other internal or external design blocks using SystemVerilog and Verilog.
- Configure and assemble SoC interconnect fabrics using AMBA AXI4, AHB, APB, and CHI protocols.
- Define and validate IP integration specifications, connectivity, configuration, clocking, resets, and interface requirements.
- Own and execute static RTL quality and sign-off flows, including Lint, CDC, RDC, and low-power intent checks.
- Work with tools such as SpyGlass, Questa CDC, VC SpyGlass, or equivalent static verification platforms.
- Develop, maintain, and validate SDC timing constraints for top-level and subsystem designs.
- Collaborate closely with Synthesis and Physical Design teams to resolve timing, area, congestion, and power-related issues.
- Analyse integration and implementation results and drive corrective actions across relevant design teams.
- Drive functional and timing ECOs during late stages of the deve

📌 Senior RTL Integration Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru