We are looking for an experienced Senior ASIC RTL Design Engineer to join our growing semiconductor design team. The ideal candidate will have strong experience in RTL development, micro-architecture design, and SoC integration.
Location: Bangalore/Hyderabad
Experience: 8–15 Years
? Key Responsibilities:
- Design and develop synthesizable RTL using Verilog/System Verilog
- Translate architecture specifications into micro-architecture and RTL implementation
- Develop high-performance and low-power digital design blocks
- Work closely with verification teams for functional validation and debug
- Perform design reviews and ensure coding quality and design guidelines
- Collaborate with physical design teams to meet timing, power, and area requirements
- Debug RTL issues and support silicon bring-up when required
? Required Skills:
- Strong expertise in Verilog and System Verilog
- Solid understanding of digital design fundamentals and computer architecture
- Experience with AMBA protocols such as AXI, AHB, and APB
- Knowledge of synthesis, timing closure,
and low-power design techniques
- Familiarity with simulation and debugging tools
- Experience working in ASIC/SoC design environments
? Preferred Qualifications:
- Strong debugging and problem-solving skills
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
- Strong understanding of digital logic design principles.
About us:
Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an productive turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silic