Hiring: Senior Physical Design Engineer – 5+ Years

Location: Bengaluru

Experience: 5+ Years

Notice Period: Immediate to 30 Days preferred

Domain: VLSI / Physical Design / Low Power

Job Summary

We are looking for an experienced Physical Design Engineer with 5+ years of hands-on experience in end-to-end Physical Design implementation, with strong expertise in Fusion Compiler (FC) and/or Cadence Innovus. The ideal candidate should have good exposure to low-power design methodologies, PPA optimization, timing closure, and physical implementation.

Key Responsibilities

- Perform end-to-end Physical Design activities from Netlist to GDSII.
- Work on Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Signoff.
- Implement and optimize designs using Synopsys Fusion Compiler (FC) and/or Cadence Innovus.
- Work on low-power design methodologies including Multi-Voltage (MV), Power Domains, Isolation Cells, Level Shifters, and Power Gating.
- Perform timing analysis and closure for setup and hold violations.
- Optimize PPA (Power, Performance, and Area) throughout the implementation flow.
- Handle MMMC constraints and scenario-based timing analysis.
- Work on congestion analysis and optimization.
- Perform CTS implementation and clock optimization.
- Resolve DRC, LVS, antenna, and other physical design violations.
- Support IR drop and electromigration (EM) analysis and signoff activities.




- Debug physical and timing issues and coordinate with STA, Synthesis, DFT, and RTL teams.
- Develop and maintain Tcl/Perl/Python automation scripts for flow enhancement and productivity.
- Participate in design reviews and contribute to methodology improvements.

Required Technical Skills

- 5+ years of hands-on experience in Physical Design.
- Robust experience in Fusion Compiler (FC) and/or Innovus.
- Good understanding of Low Power Design concepts and implementation.
- Strong knowledge of:
- Floorplanning & Power Planning
- Placement Optimization
- Clock Tree Synthesis
- Routing
- Timing Closure
- Congestion Optimization
- Physical Signoff
- Good understanding of UPF/low-power implementation concepts.
- Experience with STA and MMMC.
- Knowledge of ECO implementation and timing optimization.
- Exposure to IR/EM and physical verification is preferred.
- Strong scripting skills in Tcl; Perl/Python knowledge is an advantage.

Education

- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related engineering discipline.

Preferred Candidate Profile

- Strong hands-on implementation experience in advanced-node designs.
- Experience working on high-performance, low-power SoC designs.
- Good debugging and problem-solving skills.
- Ability to work independently and collaborate effectively with cross-functional teams.

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru