- Bachelors / Masters degree in engineering from EEE / EC with expertise in ASIC Verification or Digital Verification
- Expertise in VIP integration
- Expertise in ARM process
- Expertise in DDR ( 4 or 5 controller with Phy) / Ethernet (100 G or 2002 G) / PCIe (Gen 5 or 6) protocol
- Expertise in SOC / IP / sub-system level Verification
- Expertise in working on system Verilog assertions test benches
- Expertise in working on OVM / UVM / VMM based verification flow
- Valuable knowledge in gate-level simulation, and Scripting languages like Python, TCL
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