ACL Digital is looking for a Physical Design Lead in Bangalore to drive block and full-chip implementation from netlist to GDSII on sub-7nm/5nm/3nm nodes. In this role, you will lead hands-on floorplanning, CTS, PnR, STA, agile/static power optimization, and physical sign-off (DRC/LVS/IR drop) using Synopsys (ICC2, PrimeTime) or Cadence (Innovus, Tempus) flows. We are seeking technical leaders skilled in TCL/Python automation who can mentor engineers and manage tapeout risk across cross-functional teams.
Notice period of 0–60 days, send your resume to [email protected] to apply!