Hiring: Lead Physical Design Engineer – 8+ Years

Location: Bengaluru

Experience: 8+ Years

Notice Period: Immediate to 30 Days preferred

Domain: VLSI / Physical Design / Low Power / SoC

Job Summary

We are seeking a highly experienced Senior/Lead Physical Design Engineer with 8+ years of expertise in advanced Physical Design implementation and low-power SoC designs. The candidate should have strong hands-on experience with Synopsys Fusion Compiler (FC) and/or Cadence Innovus, along with proven expertise in PPA optimization, timing closure, low-power implementation, and physical signoff.

Key Responsibilities

- Lead and execute end-to-end Physical Design implementation from Netlist to GDSII.
- Own physical implementation activities including:
- Floorplanning
- Power Planning
- Placement
- CTS
- Routing
- ECO
- Physical Signoff
- Drive implementation using Fusion Compiler (FC) and/or Cadence Innovus.
- Lead low-power implementation across multiple voltage and power domains.
- Work with UPF-based low-power methodologies, including:
- Power Domains
- Isolation Cells
- Level Shifters
- Retention Cells
- Power Gating
- Drive PPA optimization and identify opportunities for power, performance, and area improvement.
- Own timing closure across multiple modes and corners.
- Debug and resolve complex setup/hold, congestion, clock, and routing issues.
- Lead MMMC implementation and timing optimization.
- Drive CTS and clock optimization for high-performance designs.
- Analyze and resolve DRC, LVS, antenna, density, and other physical violations.
- Work closely with STA, RTL, Synthesis, DFT, PDN/IR-EM, and Physical Verification teams.
- Support IR drop, EM, power integrity, and signoff closure.




- Develop and improve Tcl/Perl/Python-based automation for implementation and signoff flows.
- Provide technical guidance and mentorship to junior and mid-level engineers.
- Participate in methodology development, flow improvement, technical reviews, and project planning.
- Identify risks, track physical design milestones, and drive issues to closure.

Required Technical Skills

- 8+ years of strong hands-on experience in Physical Design.
- Expert-level knowledge of Fusion Compiler (FC) and/or Cadence Innovus.
- Strong experience in Low Power Design and implementation.
- Excellent understanding of:
- Advanced Floorplanning
- Power Distribution Network
- Placement Optimization
- CTS
- Routing
- Timing Closure
- Congestion Management
- ECO Implementation
- Physical Signoff
- Robust knowledge of UPF and multi-voltage design implementation.
- Strong experience with MMMC and STA concepts.
- Good understanding of IR/EM, DRC, LVS, antenna, and physical verification.
- Experience with advanced-node SoC implementation.
- Strong scripting skills in Tcl; Perl/Python is an added advantage.

Leadership & Collaboration

- Ability to independently own blocks or full-chip implementation activities.
- Strong problem-solving and analytical skills.
- Ability to lead technical discussions and resolve complex implementation issues.
- Experience mentoring engineers and coordinating with cross-functional teams.
- Strong communication and project execution skills.

Education

- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related engineering discipline.

Preferred Experience Candidates with experience in high-performance, low-power SoCs, advanced technology nodes, multi-voltage designs, and complex timing closure will be preferred.

📌 Lead Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru