Hiring for DFT Senior Engineer 9+ years

Looking for an experienced DFT Engineer with 9+ years of industry experience in ASIC/SoC Design for Test (DFT) implementation and validation. The candidate will be responsible for architecting, implementing, and verifying DFT solutions for complex SoCs.

Key Responsibilities

- Define and implement DFT architecture for complex SoCs.
- Integrate and verify Scan, MBIST, Boundary Scan (JTAG), and compression logic.
- Perform DFT rule checks, ATPG pattern generation, and pattern validation.
- Analyze test coverage, debug coverage issues, and drive closure.
- Develop and maintain DFT flows, scripts, and automation.
- Support post-silicon bring-up and production testing activities.
- Work closely with RTL, Verification, Physical Design, and Product Engineering teams.
- Ensure successful DFT sign-off and tape-out readiness.





Mandatory Skills ✅ 9+ years of hands-on DFT experience

✅ Robust expertise in:

- Scan Insertion and Scan Compression
- ATPG and Fault Coverage Analysis
- MBIST Implementation and Verification
- JTAG / IEEE 1149.1
- DFT DRC and Debug
- SoC-level DFT Integration

Educational Qualification
- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related disciplines.

Notice period : Any

Location: Open to discuss

Interested candidates can share their updated resume along with the following details:

- Name
- Contact
- Email id
- Current Company
- Total Experience
- Relevant DFT Experience
- Current CTC
- Expected CTC
- Notice Period / LWD
- Current Location
- Preferred Location

? Email: [email protected]

📌 DFT Senior Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru