We are looking for an experienced DFT Engineer with 7+ years of hands-on experience in Design for Testability for ASIC/SoC products. The ideal candidate should have strong expertise in MBIST, ATPG, and Scan Insertion/Scan Architecture and should be capable of owning DFT activities from architecture and implementation through pattern generation and verification.
Key Responsibilities:
Develop and implement DFT architecture for complex ASIC/SoC designs.
Work on Scan Insertion, Scan Architecture, and Scan Chain implementation.
Develop and debug ATPG patterns for stuck-at, transition, and other fault models.
Work on MBIST implementation and verification for embedded memories.
Analyze and improve test coverage, fault simulation, and pattern quality.
Perform DFT rule checks and identify/resolve DFT-related design violations.
Integrate DFT logic into RTL/netlist and support synthesis and physical implementation teams.
Debug scan-chain, ATPG, MBIST,
and test-coverage issues.
Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.
Support DFT verification, pattern simulation, and bring-up activities.
Review DFT requirements and contribute to test strategy and methodology development.
Document DFT implementation, test coverage, debug results, and sign-off activities.
Required Skills:
7+ years of experience in DFT / Design for Testability.
Strong hands-on experience in:
MBIST
ATPG
Scan Insertion / Scan Architecture
Scan chain design and debugging
DFT rule checking and coverage analysis
Positive understanding of ASIC/SoC DFT methodologies.
Experience with ATPG fault models such as Stuck-at and Transition.
Strong knowledge of DFT verification and pattern simulation.
Good understanding of RTL-to-GDSII design flow and interaction with synthesis/physical design.
Strong debugging and problem-solving skills.
Experience with industry-standard DFT/ATPG tools is preferred.