Role Description The DFT Engineer role at ASIP Technologies is a full-time, on-site position based in Hyderabad. The DFT Engineer will design, implement, and validate DFT structures for complex SoC designs, collaborating with RTL Design, Verification, BE Implementation and Test Engineering teams.

Day-to-day responsibilities include Insertion and Verification of DFT structures (including TAP/Scan Architecture, JTAG, MBIST, etc.), Scan Synthesis, ATPG Execution, Scan Coverage Analysis. The role includes cross-functional collaboration with Frontend Design, Verification, Physical Design, Timing closure teams to resolve all DFT-related issues and contribute to the continuous improvement of the quality of the Test patterns. The role also includes developing and reviewing Test Plans, generating and optimizing Test Program, enabling Structural Test coverage and supporting Test Bringup on ATE.

Qualifications





- Candidates should possess robust skills in DFT Architecture and Concepts with hands-on experience in Implementation, Verification, Pattern Generation and Simulation of all DFT structures
- Candidates should possess deep understanding of TAP, JTAG, Scan Arch, Scan Synthesis, ATPG, Low Coverage Debug, Memory BIST & Boundary Scan
- Experience with ATE (Automated Test Equipment), Test Program Development, Scripting (e.g., Python, TCL), and data analysis tools is preferred
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field is required
- Ability to collaborate in cross-functional teams, communicate clearly and work systematically
- Familiarity with multiple industry-standard EDA tools and version control systems is preferred

📌 DFT Engineer (Hyderabad)
🏢 ASIP Technologies
📍 Hyderabad