- Extensive experience (15+ years) in ASIC design and verification, with a focus on high-speed protocols.
- Robust proficiency in Verilog, VHDL, and/or SystemVerilog for hardware design and verification.
- Hands-on knowledge of verification methodologies such as UVM, including environment architecture and coverage analysis.
- Experience with scripting languages (BASH, TCSH, PERL, PYTHON, TCL) for automation and workflow optimization.
- Proven ability to manage and lead high-performing engineering teams in fast-paced environments.
- Exceptional problem-solving skills and attention to detail.
📌 ASIC Digital Design, Sr Manager (Noida)
🏢 Synopsys
📍 Noida
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