RTL Design Engineer | 5-12 YearsWe are seeking an RTL Design Engineer with 5-12 years of ASIC/SoC design experience to drive the development of high-performance digital designs from architecture to implementation.Key Requirements:Strong experience in RTL design using Verilog/SystemVerilog or VHDLHands-on experience in ASIC/SoC developmentStrong understanding of digital design concepts, including combinational logic, sequential logic, and FSMsExperience in functional verification and RTL debuggingKnowledge of timing analysis, timing closure, and SDC constraints, Lint/CDC.Ability to collaborate with Design, Verification, and Synthesis teams throughout the development cycleGood to Have:Exposure to UVM-based verification environmentsExperience with Python, Perl,



or Shell scriptingFamiliarity with STA and synthesis flowsQualification:Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a related fieldWhy Join Us?Opportunity to work on cutting-edge ASIC/SoC technologiesCollaborative and quick-paced engineering environmentStrong learning and career growth opportunitiesCompetitive compensation and benefits packageInterested professionals can forward their resumes to [email protected] for further discussion.

📌 Rtl Design Engineer Role (Bengaluru)
🏢 HCLTech
📍 Bengaluru