Job DescriptionWe're Hiring! Senior RTL (ASIC) Engineers at ACL Digital NOpen Requirement: Nn Experience: 6+ years in RTL Design. N Availability: We are looking for candidates who can join us on a short notice period. NnAre you an expert in ASIC front-end design with a passion for building complex SoCs? ACL Digital is expanding its VLSI design team, and we are looking for high-caliber RTL (ASIC) Engineers to join our team. NWho we are looking for: NWe are seeking experienced professionals (6+ years) who have a strong foundation in the complete ASIC design flow and can hit the ground running on our current project pipeline. NCore Responsibilities & Technical Skills: Nn Design & Coding: Robust expertise in RTL coding using Verilog/SystemVerilog and micro-architecture development. N Static Verification: Deep hands-on experience with Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis. N Tools:



Proficient in tools such as Synopsys SpyGlass, Questa, or similar static verification platforms. N ASIC Flow: Knowledge of synthesis, Logical Equivalence Checking (LEC), and full-chip integration. N Protocols: Experience with standard protocols (AMBA AXI/AHB/APB) is highly desirable. NnWhy Join ACL Digital? NBe part of a high-growth environment working on advanced node (3nm/5nm) semiconductor projects alongside industry leaders. We value technical depth, ownership, and cutting-edge problem-solving. NHow to Apply: NInterested candidates, please share your updated resume at [email protected] or reach out via DM for more details. N#Hiring #VLSIJobs #RTLDesign #ASIC #SemiconductorJobs #ACLDigital #DFT #TechCareers #ImmediateJoiners #ASICDesign

📌 Senior Rtl Engineer (Vasanthanagar)
🏢 ACL Digital
📍 Vasanthanagar