Hiring: Senior DFT Engineer | Bangalore | 8+ Years Experience
We are looking for an experienced Senior DFT (Design for Testability) Engineer to join our growing semiconductor team in Bangalore. If you have robust expertise in DFT architecture, scan implementation, MBIST, and boundary scan methodologies, we'd love to connect with you!
Key Responsibilities:-
Define and implement Scan Architecture, including EDT/OCC integration.
Perform DFT implementation, debug, and analysis across complex SoC designs.
Execute and validate Memory & IP Test Simulations involving:
MBIST
IJTAG
Boundary Scan (JTAG)
Drive pattern generation, validation, and retargeting activities.
Collaborate with design, verification, and physical design teams to ensure high-quality DFT deliverables.
Interested candidates can share their updated resume at
[email protected]
📌 Senior DFT Engineer (Vasanth Nagar)
🏢 Scaledge Technology
📍 Vasanth Nagar