About Tylsemi

Tylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution.
Role Overview

As a Design Verification Engineer at Tylsemi, you will help ensure functional correctness, robustness, and tapeout readiness of complex IPs and SoCs. You’ll work closely with design, architecture, firmware, and validation teams to build scalable verification settings, drive coverage closure, and deliver high-signal debug. This role is open across experience levels (0–30 years) and is ideal for engineers who enjoy rigorous problem solving, automation, and building verification flows that scale across programs.
What You’ll Do
Own verification execution for IP and/or SoC blocks from testplan through signoff: bring-up, regressions, coverage, and closure
Develop and maintain verification environments (e.g., SystemVerilog/UVM or equivalent methodologies aligned to the project needs)
Create high-quality testplans:



requirements traceability, scenario definition, corner cases, and measurable coverage goals
Write directed and constrained-random tests; build reusable sequences, scoreboards, monitors, and checkers
Drive functional coverage and code coverage closure; identify gaps and propose targeted stimulus and assertions
Debug failures across simulation and emulation/prototyping (as applicable): isolate root cause, propose fixes, and validate resolution
Build and scale regression infrastructure: test selection, triage workflows, failure bucketing, and signal-to-noise improvements
Automate repetitive verification tasks (Python/Perl/Tcl/Make or similar) to improve predictability and turnaround time
Leverage AI-assisted tools to accelerate debug, log triage, test generation, and documentation—while maintaining engineering rigor and reproducibility
Partner with design/architecture to clarify specs

📌 Design Verification Bengaluru
🏢 tylsemi
📍 Bengaluru