About Tylsemi
Tylsemi is building and scaling high-impact semiconductor operations. We partner across design, manufacturing, and supply chain to bring silicon from concept to high-volume production with speed, quality, and predictable execution.
Role Overview
As Design Team Member at Tylsemi, you will drive the implementation of digital blocks and/or full-chip designs from netlist to tapeout, partnering closely with RTL, verification, DFT, and signoff teams. This role is open across experience levels (0–30 years) and is ideal for leaders and engineers who enjoy solving complex timing, power, and physical constraints to deliver manufacturable, high-quality silicon.
What You’ll Do
Own physical implementation for blocks/subsystems/top-level: floorplanning, power planning, placement, CTS, routing, and ECO closure
Develop and refine constraints (SDC) in collaboration with RTL/STA; ensure constraints are consistent, complete, and implementation-ready
Drive timing closure across modes/corners, including setup/hold closure, clock quality, and path optimization




Close physical signoff requirements: DRC/LVS, IR drop/EM, antenna, density/fill, and manufacturability checks
Analyze and resolve congestion, utilization, and routing challenges; propose floorplan/architecture improvements when needed
Partner with STA and signoff teams to debug violations and implement clean, reviewable ECOs
Collaborate with DFT on scan/MBIST/DFT constraints and physical requirements; ensure implementation supports testability goals
Support low-power implementation (UPF/CPF intent awareness), multi-voltage domains, level shifters/isolation, and power gating as applicable
Create and maintain flow automation, checks, and reporting (Tcl/Python) to improve predictability and execution speed
Contribute to tapeout readiness: documentation, checklists, design reviews, and root-cause analysis of issues to prevent recurrence

What We’re Looking For
Hands-on experience with ASIC physical d

📌 Physical Design Bengaluru (India)
🏢 tylsemi
📍 India