Location: Coimbatore
Work Mode: Onsite
Employment Type: Full-Time
Experience: 8–12+ Years
Domain: Semiconductor / ASIC / SoC / VLSI
Job Summary
Zenpiya is looking for an experienced DFT Lead / Lead DFT Engineer to drive Design-for-Test architecture, implementation, verification, and signoff for complex ASIC/SoC designs.
The candidate will provide technical leadership across the complete DFT lifecycle, from DFT planning and scan insertion through ATPG, coverage improvement, gate-level simulation, pattern validation, and silicon bring-up.
Key Responsibilities
Own and drive the DFT architecture and implementation for complex ASIC/SoC designs.
Define DFT strategies covering:
Scan
Scan Compression
Analyze and improve ATPG fault coverage.
Debug DFT DRC violations,
coverage issues and pattern failures.
Perform gate-level simulations including:
Zero-delay simulation
SDF/timing simulation
Generate, validate and deliver ATE test patterns.