Job Description
Senior DFT Engineer – Bangalore
nExperience: 3+ Years
nLocation: Bangalore
nKey Responsibilities:
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Design and implement DFT solutions for complex SoC designs.n
Hands-on experience in Scan, ATPG, MBIST, JTAG and DFT DRC/debug.n
Perform scan insertion, ATPG pattern generation, fault coverage analysis and optimization.n
Experience with MBIST insertion, verification, pattern generation and debug.n
Debug DFT simulations, tester failures and support silicon bring-up/post-silicon debug.n
Collaborate with RTL, Design, Verification and Physical Design teams.n
Contribute to DFT flow automation and methodology improvements.n
nRequired Skills :
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Solid understanding of ASIC/SoC DFT flow and methodologies.n
Hands-on experience with Tessent / TetraMAX / TestMAX / Synopsys SMS.n
Valuable knowledge of ATPG, Scan, MBIST, JTAG, IEEE 1500 and OCC.n
Experience with VCS / Verdi / Xcelium / Questa simulation and debug.n
Knowledge of Verilog/SystemVerilog.n
Scripting skills in TCL / Perl / Python.n
Solid debugging, analytical and problem-solving skills.n
nEducation: B.E./B.Tech/M.E./M.Tech in ECE, Electrical & Electronics, or VLSI.