Job Description
Requisition- SoC DFT Lead
nExperience-10+ Years
nLocation- Bangalore
n
n
Tessent based SSN insertion at block or Top leveln
SSN validationn
SSN insertion expertisen
Tessent MBIST insertionn
Responsible for Implementing and integrating scan insertion, scan compression, MBIST, OCC and boundary scan at gate/RTL level.n
Team Handling Skill is preferred.n

nKey Responsibilities
nSoC DFT Architecture & Leadership
n Own SoC-level DFT architecture and strategy for custom and platform-based
nSoCs.
n Define and drive DFT implementation plans across multiple concurrent SoC
nprograms.
n Act as the technical authority and signoff owner for all DFT-related decisions and
ndeliverables.
nExecution & Technical Ownership
n Lead DFT RTL integration, scan insertion, and test architecture implementation.
n Own and drive:
n Scan, Compression, and ATPG strategy
n MBIST, BISR, and redundancy implementation
n JTAG / TAP, Boundary Scan, and debug infrastructure
n Ensure DFT readiness across functional, scan, and low-power modes.




n Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and
nimplementation.
n Drive ATPG pattern generation, simulation, and debug to ensure high test
ncoverage and quality.
nCross-Functional & Manufacturing Interface
n Work closely with physical design teams to ensure scan and test logic closure
nwith minimal PPA impact.
n Interface with manufacturing, ATE, and OSAT teams on test requirements, vector
ndelivery, and silicon bring-up.
n Support post-silicon debug, yield ramp, and test optimization.
n Represent in customer-facing technical discussions related to DFT
nstrategy and signoff.
nMethodology & Team Development
n Define and standardize DFT methodologies, flows, and checklists across
nprograms.
n Drive automation, scripting, and reuse to improve DFT efficiency and
npredictability.
n Mentor and develop DFT engineers and leads, building deep technical and


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