Senior DFT Engineer – Bangalore

nExperience: 3+ Years

nLocation: Bangalore

nKey Responsibilities:

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Design and implement DFT solutions for complex SoC designs.
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Hands-on experience in Scan, ATPG, MBIST, JTAG and DFT DRC/debug.
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Perform scan insertion, ATPG pattern generation, fault coverage analysis and optimization.
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Experience with MBIST insertion, verification, pattern generation and debug.
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Debug DFT simulations, tester failures and support silicon bring-up/post-silicon debug.
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Collaborate with RTL, Design, Verification and Physical Design teams.
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Contribute to DFT flow automation and methodology improvements.
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nRequired Skills :

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Robust understanding of ASIC/SoC DFT flow and methodologies.
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Hands-on experience with Tessent / TetraMAX / TestMAX / Synopsys SMS.
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Positive knowledge of ATPG, Scan, MBIST, JTAG, IEEE 1500 and OCC.
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Experience with VCS / Verdi / Xcelium / Questa simulation and debug.
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Knowledge of Verilog/SystemVerilog.
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Scripting skills in TCL / Perl / Python.
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Robust debugging, analytical and problem-solving skills.
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nEducation: B.E./B.Tech/M.E./M.Tech in ECE, Electrical & Electronics, or VLSI.

📌 Dft Engineer Bengaluru (India)
🏢 Mirafra Technologies
📍 India