Are you passionate about power integrity and sign-off for advanced digital SoCs? We're looking for an experienced PDN / EMIR Engineer to join our growing VLSI team.
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Required Experience
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8+ years of overall VLSI/Physical Design experience is preferred.
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3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs.
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Solid expertise with industry-standard EMIR analysis and sign-off methodologies.
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Excellent debugging, analytical, and cross-functional collaboration skills.
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Key Responsibilities
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Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs.
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Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
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Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off.
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Collaborate closely with the Physical Design (PD) team to drive effective IR/EM closure across the chip.
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Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
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Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets.
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