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Experience in Logic design / RTL coding is a must.
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Experience in SoC design and integration for complex SoCs is a must.
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Experience in Verilog/System-Verilog is a must.
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Experience in multi-clock designs and asynchronous interfaces is a must.
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Experience in using the tools in ASIC development such as Lint and CDC.
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Experience in Synthesis / Understanding of timing concepts is a plus.
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Experience in ECO fixes and formal verification.
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Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
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Excellent oral and written communication skills.
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Proactive, creative, curious, motivated to learn and contribute, with positive collaboration skills
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