Design Technology Co-Optimization Engineer, Google Cloud (Bengaluru)

Design Technology Co-Optimization Engineer, Google Cloud (Bengaluru)

18 Sep
|
Google
|
Bengaluru

18 Sep

Google

Bengaluru

Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience in Physical Design (e.g., Register-Transfer Level- to-Graphic Database System (RTL-to-GDS)) or technology development focusing on advanced nodes (e.g., 7nm, 5nm, or below).
- Experience with scripting and automation using Tcl, Python or Perl

Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Complementary Metal-Oxide-Semiconductor (CMOS) device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.
- Experience in DTCO, including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
- Experience using industry standard tools for synthesis, place and route, static timing analysis, transistor level design in advanced finfet technology nodes,



including SPICE simulations.
- Experience working with major foundry technology files (PDKs) and interpreting Design Rule Manuals (DRM) to guide physical implementation.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Technology Co-Optimization (DTCO) Engineer, you will bridge the gap between process technology and product architecture to define the next generation of data center-class silicon. You will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures. You will conduct rigorous Place and Route

📌 Design Technology Co-Optimization Engineer, Google Cloud (Bengaluru)
🏢 Google
📍 Bengaluru

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