Key Skills:

Architecture, Communication, Design, EDA, Go, Linux, RTL, SAP, SoC

Roles and Responsibilities:

- Define DFT architecture for next-generation Arm IPs and SoCs, including emerging AI and hyperscale computing products.

- Develop and drive scalable DFT methodologies and implementation flows used across multiple Arm engineering organizations.

- Evaluate emerging DFT technologies and lead technical investigations to solve future product challenges.

- Collaborate with architecture, implementation, verification and physical design teams to define robust DFT solutions.

- Work closely with EDA vendors to influence product roadmaps, evaluate current capabilities and drive adoption of new technologies.

- Produce architecture specifications, methodology documentation and deployment guidance.

- Provide technical leadership and mentorship across project teams.

- Support strategic engagements with customers, ASIC partners and industry standards bodies where appropriate.

- Contribute to technical publications, patents and industry conferences.

Skills Required:

- Principal or Senior Principal level engineer with extensive experience in Design-for-Test architecture and implementation.

- Strong understanding of modern SoC DFT methodologies including:Scan architecture and scan compression

- ATPG and fault simulation

- At-speed testing

- Memory BIST

- Logic BIST

- JTAG / IEEE 1149.1

- IJTAG / IEEE 1687





- DFT verification and debug

- Experience developing reusable DFT methodologies or automation rather than project-specific solutions.

- Experience evaluating and deploying Siemens Tessent, Synopsys and/or Cadence DFT solutions.

- Strong scripting skills (Perl, Tcl and/or Python) together with Linux/Unix expertise.

- Excellent problem-solving and analytical skills.

- Strong communication skills with the ability to influence technical direction across multiple engineering teams.

- Degree (or equivalent) in Electronic Engineering, Computer Engineering or related discipline.

“Nice To Have” Skills and Experience :

- Experience defining DFT architecture for large-scale SoCs.

- Experience with heterogeneous compute systems, AI accelerators or hyperscale computing products.

- Knowledge of IEEE 1500, IEEE 1838 and advanced IJTAG methodologies.

- Experience with Streaming Scan Network (SSN) and chiplet/3DIC architectures.

- Familiarity with silicon bring-up and production test.

- Experience working directly with EDA vendors on new technology development.

- Knowledge of synthesis, STA and physical implementation considerations for DFT.

- Experience with formal verification and simulation methodologies.

- Record of patents, conference publications or contributions to industry standards.

Education:

Bachelor's degree in Engineering

📌 Senior Principal Engineer- DFT (Bengaluru)
🏢 MyCareernet
📍 Bengaluru