Key Skills:

API, Architecture, Design, Project Management, Python, RTL, SoC, SystemVerilog, UVM

Roles and Responsibilities:

- Depending on prior experience the responsibilities of the role can include:

- Ownership of unit level development or multiple unit hierarchy or technical lead of an overall IP.

- Design and test new hardware modules to implement creative imaging algorithms and/or video codecs.

- Engage in all aspect of hardware design including architectural investigations and modeling, specifications, design and simulation, backend implementation support and IP maintenance.

- Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance the hardware design efficiency.

- Collaborate closely with colleagues in the verification teams, modelling teams, software driver developers, multimedia architects and imaging researchers.

- Mentor & support other members of the team

Skills Required:

- 15+ years of experience in ASIC RTL design, ideally for Multimedia IP (ISPs, DPUs, VPUs) or related IP (CPU, GPU, interconnect, memory controllers, high-performance peripherals).





- Proficiency in System Verilog, Verilog or VHDL.

- Exposure to all stages of design: concept, specification, implementation, testing, documentation, and support.

- Proficiency in UNIX and scripting languages such as TCL, Perl, Python, or shell scripting.

- Prior technical and/or team leadership skills required for more senior positions.

Desirable skills and experience

- Knowledge of advanced image processing algorithms, such as local tone mapping, noise reduction, motion estimation, transform coding etc or AI/ML based computer vision algorithms.

- Experience of designing to meet industry standard protocols (e.g. AMBA interfaces, DDR specifications)

- Experience of Functional Safety product development for the Automotive market (applying standards such as ISO 26262 and/or IEC 61508)

- Programming language, such MATLAB, 'C' or C++

- Experience with SystemVerilog Assertions (SVA) and Continuous Integration flows

Education:

Bachelor's degree in Engineering

📌 Principal Engineer (Bengaluru)
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