Job DescriptionDTMA & Memory Controller Design Lead

NLocation: Bangalore, India |Company: LTSCT — L&T; Semiconductor Technologies Limited

NReporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory)

NRole Summary

nThe DTMA & Memory Controller Design Lead owns the Data Transfer and Memory Access (DTMA) engine together with HBM4e memory-controller integration. You will orchestrate all data movement between the 512-bank SRAM (8 TB/s), the 6-stack HBM4e subsystem (384 GB, 12 TB/s), and the PE arrays — the subsystem that keeps xPU's compute engine saturated.

NKey Responsibilities

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- Own micro-architecture and RTL of the DTMA engine managing data movement between SRAM banks, HBM4e, and the BFOS PE arrays.
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- Define the compute-to-memory interface with the DTMA engine and SRAM banks to keep PE arrays fully fed at bandwidth.
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- Lead integration and configuration of HBM4e memory controllers across 6 stacks (384 GB, 12 TB/s aggregate).
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- Design descriptor-basedDMA, gather/scatter, tensor-tiling, and prefetch mechanisms optimized for BFOS dataflow.
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- Architect the 512-bank,8 TB/s SRAM access scheduling, bank arbitration, and conflict-avoidance logic.
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- Optimize address mapping, request scheduling, and refresh/timing to maximize sustained HBM bandwidth efficiency.
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- Define QoS and flow-control interfaces to the NoC and compute engine to prevent stalls and starvation.
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- Drive verification, performance modeling,



and bandwidth/latency closure across realistic AI workload traffic.
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- Collaborate with PD on HBM PHY/controller placement and with architecture on memory-hierarchy trade-offs.
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nRequired Skills & Experience

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- 10+ years in memory-subsystem, DMA, or memory-controller design for high-bandwidth SoCs.
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- Deep expertise with DRAM/HBM controller architecture, scheduling, and timing (HBM2E/HBM3/HBM3E;

HBM4e a solid plus).

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- Strong RTL (SystemVerilog) design skills for DMA engines, arbiters, and memory schedulers.
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- Solid understanding of multi-bank SRAM architectures, banking/interleaving, and conflict resolution.
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- Experience with descriptor-based DMA, gather/scatter, tensor tiling, and prefetching.
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- Knowledge of address mapping, request reordering, and bandwidth/efficiency optimization.
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- Familiarity with AI/ML data-movement patterns and their impact on memory-system design.
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- Hands-on performance modeling and closure for high-bandwidth memory subsystems.
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- Proficiency in C/C++/Python for modeling and verification.
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- Proven technical leadership and cross-functional collaboration.
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nPreferred Qualifications

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- Experience integrating HBM PHY/controller IP on advanced nodes.
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- Background in AI accelerator or HPC memory subsystems.
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- Familiarity with UCIe/NoC traffic interaction with memory controllers.
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- M.Tech/MS in EE/ECE or equivalent.
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📌 Dtma & Memory Controller Design Lead (Karnataka)
🏢 Lu0026T Semiconductor Technologies
📍 Karnataka