Role & Responsibilities:

Perform IP-level verification of digital/analog designs using SystemVerilog-based testbench architecture.

Develop verification plans from design specifications and implement verification scenarios.

Apply Coverage Driven Verification methodology and achieve coverage closure.

Develop and execute Constrained Random Verification scenarios.

Perform structured waveform-based and file/log-based debugging.

Collaborate with design and verification teams to identify, analyze and resolve issues.

Prepare verification documentation and communicate technical findings effectively.

Preferred candidate profile:

45 years of relevant industry experience in IP/Design Verification.

Solid hands-on experience in IP verification and SystemVerilog-based testbench architecture.

Experience with Coverage Driven Verification and Constrained Random Verification.

Strong waveform and log-based debugging skills for digital and analog designs.

Excellent written and verbal communication skills.

📌 Design and Verification Engineer (Noida)
🏢 Allegis Global Solutions (AGS)
📍 Noida