Job Description

Location: Noida/Bengaluru/Hyderabad

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Experience: 8+ Years

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Employment Type: Full-time

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Job Overview

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We are looking for an experienced Memory Circuit Design Engineer to join our semiconductor design team and work on the design and development of advanced memory circuits and memory macros.

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The ideal candidate will have strong hands-on experience in transistor-level memory circuit design, memory architecture, circuit optimization, SPICE simulation, and PVT/corner analysis. The role will involve working closely with architecture, layout, characterization, verification and physical design teams to deliver robust, high-performance and low-power memory solutions.

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Key Responsibilities

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- Design and develop memory circuits and memory macros at transistor level.
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- Work on memory architectures such as SRAM, Register File, ROM and/or DRAM, depending on project requirements.
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- Develop and optimize critical memory circuits including:
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Memory bitcells

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Sense amplifiers

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Write drivers

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Precharge/equalization circuits

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Row/column decoders

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Wordline drivers

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Column muxing

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Address buffers

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Read/write control circuits

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Assist circuits

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Timing/control circuits

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- Perform schematic design and transistor-level simulations using SPICE-based simulators.
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- Analyze memory performance across PVT corners, voltage ranges and temperature conditions.
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- Optimize memory designs for:
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Read/write performance

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Access time

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Leakage power

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Dynamic power

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Area

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Stability

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Yield and robustness

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- Perform Monte Carlo and statistical analysis to evaluate process variation and mismatch.
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- Analyze memory failure mechanisms including read stability, write ability, leakage, disturb conditions and sense-margin issues.
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- Develop and optimize memory circuits for low-voltage and low-power operation.




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- Work with layout engineers to ensure robust implementation and minimize layout-dependent effects.
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- Review and analyze post-layout simulations, including extracted parasitics.
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- Support characterization of memory macros across different PVT conditions.
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- Debug circuit-level issues and identify root causes of performance, functionality or yield degradation.
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- Collaborate with architecture, layout, verification, characterization and technology teams throughout the design cycle.
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- Contribute to design reviews, technical documentation and design methodology improvements.
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- Support silicon bring-up, silicon correlation and post-silicon debug, wherever applicable.
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Required Skills & Experience

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- 8+ years of hands-on experience in Memory Circuit Design / Memory IC Design.
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- Solid experience in transistor-level circuit design.
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- Strong understanding of CMOS circuit design and semiconductor device fundamentals.
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- Hands-on experience with one or more memory technologies:
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- SRAM
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- DRAM
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- Register File
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- ROM
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- Strong understanding of memory architecture and critical memory circuits.
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- Experience designing and optimizing bitcells and peripheral circuits.
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- Strong hands-on experience with SPICE simulations and circuit-level debugging.
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- Experience with Cadence Virtuoso and Spectre or equivalent tools.
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- Strong experience with:
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- PVT analysis
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- Monte Carlo analysis
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- Corner analysis
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- Post-layout simulation
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- Parasitic analysis
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- Understanding of memory timing and performance parameters.
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- Experience with circuit optimization for power, performance, area and robustness.
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- Strong understanding of process variation, mismatch and reliability considerations.
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- Ability to work independently on circuit design problems and drive them to closure.
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Preferred / Good-to-Have Skills

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- Experience with advanced CMOS/FinFET technology nodes.
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- Experience with high-density SRAM or embedded memory macros.
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- Experience with high-speed memory design.
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- Experience with low-voltage SRAM design.
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- Knowledge of:
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- SRAM stability
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- SNM
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- Write Margin
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- Read Margin
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- Assist techniques
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- Leakage reduction
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- Variation-aware design
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- Sense amplifier offset
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- Bitline architecture
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- Experience with DRAM peripheral circuit design, if applicable.
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- Exposure to memory compiler / memory macro development.
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- Experience with memory characterization and Liberty/model generation.
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- Familiarity with Calibre DRC/LVS/PEX and post-layout verification.
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- Experience working with advanced-node design challenges.
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- Scripting knowledge in Python, Perl, Tcl or SKILL is a plus.
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- Experience with silicon correlation and post-silicon debug is highly desirable.
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Tools

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Primary:

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- Cadence Virtuoso
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- Spectre / Spectre X / FastSPICE
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Physical Verification / Extraction:

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- Calibre
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- PEX / RC extraction tools
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Simulation / Analysis:

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- SPICE
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- Monte Carlo
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- PVT / Corner Analysis
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Scripting:

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- Python
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- Tcl
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- Perl
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- SKILL
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Education

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- B.E./B. Tech/M.E./M. Tech in Electronics & Communication, Electrical Engineering, VLSI or related disciplines.
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📌 Memory Circuit Design Lead (India)
🏢 leadIC Design
📍 India