Job Description

Requisition- SoC DFT Lead

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Experience-10+ Years

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Location- Bangalore

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- Tessent based SSN insertion at block or Top level
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- SSN validation
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- SSN insertion expertise
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- Tessent MBIST insertion
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- Responsible for Implementing and integrating scan insertion, scan compression, MBIST, OCC and boundary scan at gate/RTL level.
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- Team Handling Skill is preferred.
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Key Responsibilities

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SoC DFT Architecture & Leadership

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 Own SoC-level DFT architecture and strategy for custom and platform-based

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SoCs.

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 Define and drive DFT implementation plans across multiple concurrent SoC

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programs.

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 Act as the technical authority and signoff owner for all DFT-related decisions and

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deliverables.

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Execution & Technical Ownership

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 Lead DFT RTL integration, scan insertion, and test architecture implementation.

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 Own and drive:

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 Scan, Compression, and ATPG strategy

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 MBIST, BISR, and redundancy implementation

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 JTAG / TAP, Boundary Scan, and debug infrastructure

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 Ensure DFT readiness across functional, scan, and low-power modes.

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 Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and

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implementation.

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 Drive ATPG pattern generation, simulation, and debug to ensure high test

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coverage and quality.

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Cross-Functional & Manufacturing Interface

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 Work closely with physical design teams to ensure scan and test logic closure

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with minimal PPA impact.

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 Interface with manufacturing, ATE, and OSAT teams on test requirements, vector

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delivery, and silicon bring-up.

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 Support post-silicon debug, yield ramp, and test optimization.

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 Represent in customer-facing technical discussions related to DFT

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strategy and signoff.

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Methodology & Team Development

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 Define and standardize DFT methodologies, flows, and checklists across

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programs.

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 Drive automation, scripting, and reuse to improve DFT efficiency and

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predictability.

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 Mentor and develop DFT engineers and leads, building deep technical and

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execution capability.

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 Review and approve DFT signoff reports and tapeout readiness criteria.

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Qualifications

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 B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.

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 12+ years of experience in DFT architecture and implementation for complex

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SoCs.

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 Proven track record of leading DFT implementation and signoff on multiple

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custom SoC tapeouts.

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 Strong expertise in:

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 Scan, Compression, and ATPG methodologies

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 MBIST, BISR, and memory repair schemes

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 JTAG / TAP and Boundary Scan

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 DFT RTL integration and pattern simulation

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 Hands-on experience with industry-standard DFT tools, such as:

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 Siemens Tessent

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 Synopsys DFTMAX / TestMAX

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 SpyGlass DFT (or equivalent)

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 Solid understanding of:

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 Low-power DFT challenges (UPF/CPF)

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 Scan and test-mode timing closure

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 Physical implementation constraints for DFT

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 Experience working with manufacturing, ATE, and post-silicon validation teams.

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 Excellent problem-solving, communication, and leadership skills.

📌 Lead Engineer (Bengaluru)
🏢 Angel and Genie
📍 Bengaluru