19 Sep
|
Weekday AI
|
Bengaluru
19 Sep
Weekday AI
Bengaluru
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Experience: 7+ yrs
Location: Bengaluru
Job Type: Full time
We are looking for an experienced Senior Design Verification Engineer with strong expertise in SystemVerilog (SV) and UVM-based verification to drive verification activities for complex IP and SoC designs.
The ideal candidate will have hands-on experience executing multiple IP and SoC verification projects, developing robust verification environments, creating verification plans, debugging functional and gate-level simulations, and driving coverage closure. Experience with at least one industry-standard protocol such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR is required.
Requirements
Key Responsibilities
- Develop and execute comprehensive design verification strategies and plans for IP and SoC projects.
- Translate functional and technical requirements into detailed verification plans, test scenarios, and coverage objectives.
- Develop scalable and reusable SystemVerilog/UVM verification environments.
- Build UVM components including testbenches, agents, drivers, monitors, sequencers, scoreboards, and coverage models.
- Set up, configure, execute, and debug functional and gate-level simulations.
- Develop and maintain automated regression environments for large verification programs.
- Analyze simulation failures, identify root causes, and collaborate with RTL and design teams to resolve issues.
- Verify designs using industry-standard protocols such as Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, DDR, or equivalent protocols.
- Evaluate, integrate, configure, and validate third-party Verification IP (VIP).
- Develop effective test strategies for functional, corner-case, error, and protocol-specific scenarios.
- Perform functional and code coverage analysis and drive coverage closure.
- Identify verification gaps and develop additional tests, assertions, or coverage models where requ
📌 Design Verification Lead (Bengaluru)
🏢 Weekday AI
📍 Bengaluru