Desired Profile
Bachelors / Masters degree in engineering from EEE / EC with expertise in memory layout design
Expertise in submicron processes - 7nm, 5nm, 3nm, 2nm
Expertise in leading teams, hiring mentoring junior engineers and manage projects effectively.
Expertise in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).
Expertise in Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.
Expertise in floor-planning, hierarchy layout, and chip integration.
Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
Robust knowledge of memory layout topology;

experience with memory compilers is preferred.
Knowledge of AI, layout automation, and script/SKILL programming is preferred.
Ability to lead recent technology reviews to document layout methodologies, flows, and guidelines.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Semiconductor : People Manager, Memory Layout Odc Bengaluru
🏢 Vhunt4U
📍 Bengaluru