Desired Profile
Bachelors / Masters degree in engineering from EEE / EC with expertise in ASIC PD
Experience in Top / Block level ASIC PnR implementation (RTL to GDSII).
Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
Excellent communication and presentation skills, experience in collaborating with global teams.
Experience in hierarchical designs and/or Low Power implementation is an advantage.
Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.




Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
Ability to provide mentorship and guidance to junior engineers and be an effective team player.
Expertise in Cadence Innovus, Tempus, Calibre
Required relevant expertise for Malaysia is 5+ years and 10+ years of relevant expertise for other locations
Preferred immediate hires

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📌 Semiconductor : Physical Design Engineer Asic Bengaluru (India)
🏢 Vhunt4U
📍 India