Desired Profile
Bachelors / Masters degree in engineering from EEE / EC with expertise in ASIC STA / SYNTHESIS
Timing analysis and logic synthesis of digital designs.
Achieve timing closure and optimize design performance, power and area.
Perform RTL synthesis using industry-standard tools
Should be capable to analyze and run LEC to ensure gate level netlist matches the original RTL
Run Static Timing Analysis (STA) and identify timing violations
Fix setup and hold violations across different corners/modes
Work on constraints development (SDC creation and validation)
Analyze timing reports and improve design quality
Collaborate with RTL, DFT, and Physical Design teams
Support timing closure during implementation and signoff




Robust understanding of digital design fundamentals
Knowledge of synthesis and STA flow
Familiarity with timing concepts (setup, hold, skew, latency)
Experience with EDA tools - Genus, Tempus
Required relevant expertise for Malaysia is 5+ years and 10+ years of relevant expertise for other locations
Preferred immediate hires

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Semiconductor : Sta Synthesis & Timing Engineer Asic Bengaluru
🏢 Vhunt4U
📍 Bengaluru