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Responsible for chip level STA convergence from early stages to signoff.

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Participate in top level floor plan and clock planning.

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IP & SoC timing constraints definition for all modes including DFT

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Constraints quality check

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Multimode-multi corner timing analysis.

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Timing ECO generation.

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Block and SoC level timing convergence.

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Block and SoC level Synthesis.

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Block and SoC level equivalence check.

/n /n Experience Required: /n /n
5 to 8 years of experience in SOC level timing convergence

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Synthesis and equivalence check

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Robust timing concepts

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Working knowledge of low power design involving multiple power domains.

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Proficiency in scripting languages such as TCL, Perl, or Python for automation.

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Familiarity with industry-standard EDA tools for STA like Tempus and PrimeTime

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Exposure to complex design having multiple asynchronous clocks.

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📌 Sta Engineer Bengaluru
🏢 HrdWyr
📍 Bengaluru