Design Lead
Bangalore, Karnataka
Job Summary
Robust background in SystemVerilog and UVM.Experience in SoC verification and simulation-based validationWorking experience on GLS with Zero delay, Timing, Power-aware GLSUnderstanding of PCIe, CXL, memory hierarchy, coherency, virtualization, and security concepts.Experience with regression management and coverage closure.Strong scripting skills in Python, Perl, or Shell.Excellent debugging and analytical skills.
Key Responsibilities
SoC Pre-Si Verification/Emulation execution with specialization in Server SoC Debug fabrics like Visa, Trace, Observability, Trigger, TAP based functional testing
Skill Requirements
Strong in System Verilog/UVM, Verification debug tools, Assertions, checkers and Test codingTest execution in Pre-Silicon and emulation platform (Pyton based)
Other Requirements
Experience in Server SoC’s methodology.
📌 Design Lead (India)
🏢 HCLTech
📍 India